View AD7904BRUZ_4309247.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4-channel, 1 msps, 8-/10-/12-bit adcs with sequencer in 16-lead tssop ad7904/ad7914/ad7924 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2009 analog devices, inc. all rights reserved. features fast throughput rate: 1 msps specified for av dd of 2.7 v to 5.25 v low power: 6 mw maximum at 1 msps with 3 v supplies 13.5 mw maximum at 1 msps with 5 v supplies 4 single-ended inputs with sequencer wide input bandwidth: ad7924, 70 db snr at 50 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface: spi/qspi?/ microwire?/dsp compatible shutdown mode: 0.5 a maximum 16-lead tssop package functional block diagram agnd sclk dout din cs v drive a v dd control logic 8-/10-/12-bit successive approximation adc t/h ref in v in 0 v in 3 v in 2 v in 1 i/p mux ad7904/ad7914/ad7924 sequencer 03087-001 figure 1. general description the ad7904/ad7914/ad7924 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, low power, 4-channel successive approxi- mation adcs. the parts operate from a single 2.7 v to 5.25 v power supply and feature throughput rates up to 1 msps. the parts contain a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 mhz. the conversion process and data acquisition are controlled using cs and the serial clock signal, allowing the device to easily inter- face with microprocessors or dsps. the input signal is sampled on the falling edge of cs and conversion is also initiated at this point. there are no pipeline delays associated with the part. the ad7904/ad7914/ad7924 use advanced design techniques to achieve very low power dissipation at maximum throughput rates. at maximum throughput rates, the ad7904/ad7914/ ad7924 consume 2 ma maximum with 3 v supplies; with 5 v supplies, the current consumption is 2.7 ma maximum. through the configuration of the control register, the analog input range for the part can be selected as 0 v to ref in or 0 v to 2 ref in , with either straight binary or twos complement output coding. the ad7904/ad7914/ad7924 each feature four single- ended analog inputs with a channel sequencer to allow a pre- programmed selection of channels to be converted sequentially. the conversion time fo r the ad7904/ad7914/ad7924 is determined by the sclk frequency, which is also used as the master clock to control the conversion. product highlights 1. high throughput with low power consumption. the ad7904/ad7914/ad7924 offer throughput rates up to 1 msps. at the maximum throughput rate with 3 v supplies, the ad7904/ad7914/ad7924 dissipate only 6 mw of power maximum. 2. four single-ended inputs with channel sequencer. a consecutive sequence of channels can be selected, through which the adc will cycle and convert on. 3. single-supply operation with v drive function. the ad7904/ad7914/ad7924 operate from a single 2.7 v to 5.25 v supply. the v drive function allows the serial inter- face to connect directly to 3 v or 5 v processor systems, independent of v dd . 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the conversion time to be reduced by increasing the serial clock speed. the parts also feature two shutdown modes to maximize power efficiency at lower throughput rates. current consumption is 0.5 a maximum when in full shutdown. 5. no pipeline delay. the parts feature a standard successive approximation adc with accurate control of the sampling instant via the cs input and once-off conversion control.
ad7904/ad7914/ad7924 rev. a | page 2 of 3 2 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? ad7904 specifications ................................................................. 3 ? ad7914 specifications ................................................................. 5 ? ad7924 specifications ................................................................. 7 ? timing specifications .................................................................. 9 ? absolute maximum ratings .......................................................... 10 ? esd caution ................................................................................ 10 ? pin configuration and function descriptions ........................... 11 ? typical performance characteristics ........................................... 12 ? terminology .................................................................................... 14 ? control register .............................................................................. 15 ? sequencer operation ................................................................. 16 ? circuit information ........................................................................ 18 ? converter operation .................................................................. 18 ? adc transfer function ............................................................. 19 ? typical connection diagram ................................................... 20 ? modes of operation ....................................................................... 22 ? normal mode (pm1 = pm0 = 1) ............................................. 22 ? full shutdown mode (pm1 = 1, pm0 = 0) ............................. 22 ? auto shutdown mode (pm1 = 0, pm0 = 1) ........................... 22 ? powering up the ad7904/ad7914/ad7924 ......................... 23 ? power vs. throughput rate ........................................................... 25 ? serial interface ............................................................................ 25 ? applications information .............................................................. 27 ? microprocessor interfacing ....................................................... 27 ? grounding and layout .............................................................. 28 ? evaluating ad7904/ad7914/ad7924 performance ............ 29 ? outline dimensions ....................................................................... 30 ? ordering guide .......................................................................... 30 ? revision history 2/09rev. 0 to rev. a updated format .................................................................. universal moved figure 2 ................................................................................. 9 change to table 5 ........................................................................... 10 changes to typical performance characteristics section ......... 12 moved terminology section ......................................................... 14 updated outline dimensions ....................................................... 30 changes to ordering guide .......................................................... 30 11/02revision 0: initial version
ad7904/ad7914/ad7924 rev. a | page 3 of 3 2 specifications ad7904 specifications av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , unless otherwise noted. table 1. parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave, f sclk = 20 mhz signal to (noise + distortion) (sinad) 2 49 db min signal-to-noise ratio (snr) 49 db min total harmonic distortion (thd) 2 ?66 db max peak harmonic or spurious noise (sfdr) ?64 db max intermodulation distortion (imd) fa = 40.1 khz, fb = 41.5 khz second-order terms ?90 db typ third-order terms ?90 db typ aperture delay 10 ns typ aperture jitter 50 ps typ channel-to-channel isolation 2 ?85 db typ f in = 400 khz full power bandwidth 8.2 mhz typ @ 3 db 1.6 mhz typ @ 0.1 db dc accuracy resolution 8 bits integral nonlinearity (inl) 2 0.2 lsb max differential nonlinearity (dnl) 2 0.2 lsb max guaranteed no missed codes to 8 bits 0 v to ref in input range straight binary output coding offset error 2 0.5 lsb max offset error match 2 0.05 lsb max gain error 2 0.2 lsb max gain error match 2 0.05 lsb max 0 v to 2 ref in input range ?ref in to +ref in biased about ref in with twos complement output coding positive gain error 2 0.2 lsb max positive gain error match 2 0.05 lsb max zero code error 2 0.5 lsb max zero code error match 2 0.1 lsb max negative gain error 2 0.2 lsb max negative gain error match 2 0.05 lsb max analog input input voltage range 0 to ref in v range bit set to 1 0 to 2 ref in v range bit set to 0, av dd /v drive = 4.75 v to 5.25 v dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage 2.5 v 1% specified performance dc leakage current 1 a max ref in input impedance 36 k typ f sample = 1 msps logic inputs input high voltage, v inh 0.7 v drive v min input low voltage, v inl 0.3 v drive v max input current, i in 1 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 3 10 pf max
ad7904/ad7914/ad7924 rev. a | page 4 of 32 parameter b version 1 unit test conditions/comments logic outputs output high voltage, v oh v drive ? 0.2 v min i source = 200 a, av dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary coding bit set to 1 twos complement coding bit set to 0 conversion rate conversion time 800 ns max 16 sclk cycles with sclk at 20 mhz track-and-hold acquisition time 2 300 ns max sine wave input 300 ns max full-scale step input throughput rate 1 msps max see the serial interface section power requirements v dd 2.7/5.25 v min/v max v drive 2.7/5.25 v min/v max i dd 4 digital inputs = 0 v or v drive normal mode (static) 600 a typ av dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max av dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2 ma max av dd = 2.7 v to 3.6 v, f sclk = 20 mhz auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max static full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) 13.5 mw max av dd = 5 v, f sclk = 20 mhz 6 mw max av dd = 3 v, f sclk = 20 mhz auto shutdown mode (static) 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v full shutdown mode 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v 1 temperature range for b versions: ?40c to +85c. 2 see the terminology section. 3 sample tested @ 25c to ensure compliance. 4 see the power vs. throughput rate section.
ad7904/ad7914/ad7924 rev. a | page 5 of 32 ad7914 specifications av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , unless otherwise noted. table 2. parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave, f sclk = 20 mhz signal to (noise + distortion) (sinad) 2 61 db min signal-to-noise ratio (snr) 61 db min total harmonic distortion (thd) 2 ?72 db max peak harmonic or spurious noise (sfdr) ?74 db max intermodulation distortion (imd) fa = 40.1 khz, fb = 41.5 khz second-order terms ?90 db typ third-order terms ?90 db typ aperture delay 10 ns typ aperture jitter 50 ps typ channel-to-channel isolation 2 ?85 db typ f in = 400 khz full power bandwidth 8.2 mhz typ @ 3 db 1.6 mhz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity (inl) 2 0.5 lsb max differential nonlinearity (dnl) 2 0.5 lsb max guaranteed no missed codes to 10 bits 0 v to ref in input range straight binary output coding offset error 2 2 lsb max offset error match 2 0.2 lsb max gain error 2 0.5 lsb max gain error match 2 0.2 lsb max 0 v to 2 ref in input range ?ref in to +ref in biased about ref in with twos complement output coding positive gain error 2 0.5 lsb max positive gain error match 2 0.2 lsb max zero code error 2 2 lsb max zero code error match 2 0.2 lsb max negative gain error 2 0.5 lsb max negative gain error match 2 0.2 lsb max analog input input voltage range 0 to ref in v range bit set to 1 0 to 2 ref in v range bit set to 0, av dd /v drive = 4.75 v to 5.25 v dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage 2.5 v 1% specified performance dc leakage current 1 a max ref in input impedance 36 k typ f sample = 1 msps logic inputs input high voltage, v inh 0.7 v drive v min input low voltage, v inl 0.3 v drive v max input current, i in 1 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 3 10 pf max logic outputs output high voltage, v oh v drive ? 0.2 v min i source = 200 a, av dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 1 a max
ad7904/ad7914/ad7924 rev. a | page 6 of 32 parameter b version 1 unit test conditions/comments floating-state output capacitance 3 10 pf max output coding straight (natural) binary coding bit set to 1 twos complement coding bit set to 0 conversion rate conversion time 800 ns max 16 sclk cycles with sclk at 20 mhz track-and-hold acquisition time 2 300 ns max sine wave input 300 ns max full-scale step input throughput rate 1 msps max see the serial interface section power requirements v dd 2.7/5.25 v min/v max v drive 2.7/5.25 v min/v max i dd 4 digital inputs = 0 v or v drive normal mode (static) 600 a typ av dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max av dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2 ma max av dd = 2.7 v to 3.6 v, f sclk = 20 mhz auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max static full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) 13.5 mw max av dd = 5 v, f sclk = 20 mhz 6 mw max av dd = 3 v, f sclk = 20 mhz auto shutdown mode (static) 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v full shutdown mode 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v 1 temperature range for b versions: ?40c to +85c. 2 see the terminology section. 3 sample tested @ 25c to ensure compliance. 4 see the power vs. throughput rate section.
ad7904/ad7914/ad7924 rev. a | page 7 of 32 ad7924 specifications av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , unless otherwise noted. table 3. parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave, f sclk = 20 mhz signal to (noise + distortion) (sinad) 2 70 db min @ 5 v 69 db min @ 3 v, typically 69.5 db signal-to-noise ratio (snr) 70 db min total harmonic distortion (thd) 2 ?77 db max @ 5 v, typically ?84 db ?73 db max @ 3 v, typically ?77 db peak harmonic or spurious noise (sfdr) ?78 db max @ 5 v, typically ?86 db intermodulation distortion (imd) fa = 40.1 khz, fb = 41.5 khz second-order terms ?90 db typ third-order terms ?90 db typ aperture delay 10 ns typ aperture jitter 50 ps typ channel-to-channel isolation 2 ?85 db typ f in = 400 khz full power bandwidth 8.2 mhz typ @ 3 db 1.6 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity (inl) 2 1 lsb max differential nonlinearity (dnl) 2 ?0.9/+1.5 lsb max guaranteed no missed codes to 12 bits 0 v to ref in input range straight binary output coding offset error 2 8 lsb max typically 0.5 lsb offset error match 2 0.5 lsb max gain error 2 1.5 lsb max gain error match 2 0.5 lsb max 0 v to 2 ref in input range ?ref in to +ref in biased about ref in with twos complement output coding positive gain error 2 1.5 lsb max positive gain error match 2 0.5 lsb max zero code error 2 8 lsb max typically 0.8 lsb zero code error match 2 0.5 lsb max negative gain error 2 1 lsb max negative gain error match 2 0.5 lsb max analog input input voltage range 0 to ref in v range bit set to 1 0 to 2 ref in v range bit set to 0, av dd /v drive = 4.75 v to 5.25 v dc leakage current 1 a max input capacitance 20 pf typ reference input ref in input voltage 2.5 v 1% specified performance dc leakage current 1 a max ref in input impedance 36 k typ f sample = 1 msps logic inputs input high voltage, v inh 0.7 v drive v min input low voltage, v inl 0.3 v drive v max input current, i in 1 a max typically 10 na, v in = 0 v or v drive input capacitance, c in 3 10 pf max
ad7904/ad7914/ad7924 rev. a | page 8 of 32 parameter b version 1 unit test conditions/comments logic outputs output high voltage, v oh v drive ? 0.2 v min i source = 200 a, av dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary coding bit set to 1 twos complement coding bit set to 0 conversion rate conversion time 800 ns max 16 sclk cycles with sclk at 20 mhz track-and-hold acquisition time 2 300 ns max sine wave input 300 ns max full-scale step input throughput rate 1 msps max see the serial interface section power requirements v dd 2.7/5.25 v min/v max v drive 2.7/5.25 v min/v max i dd 4 digital inputs = 0 v or v drive normal mode (static) 600 a typ av dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) 2.7 ma max av dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2 ma max av dd = 2.7 v to 3.6 v, f sclk = 20 mhz auto shutdown mode 960 a typ f sample = 250 ksps 0.5 a max static full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) 13.5 mw max av dd = 5 v, f sclk = 20 mhz 6 mw max av dd = 3 v, f sclk = 20 mhz auto shutdown mode (static) 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v full shutdown mode 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v 1 temperature range for b versions: ?40c to +85c. 2 see the terminology section. 3 sample tested @ 25c to ensure compliance. 4 see the power vs. throughput rate section.
ad7904/ad7914/ad7924 rev. a | page 9 of 32 timing specifications av dd = 2.7 v to 5.25 v, v drive av dd , ref in = 2.5 v, t a = t min to t max , unless otherwise noted. table 4. parameter 1 limit at t min , t max description av dd = 3 v av dd = 5 v unit f sclk 2 10 10 khz min 20 20 mhz max t convert 16 t sclk 16 t sclk t quiet 50 50 ns min minimum quiet time required between the cs rising edge and the start of the next conversion t 2 10 10 ns min cs to sclk setup time t 3 3 35 30 ns max delay from cs until dout three-state disabled t 4 3 40 40 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 7 10 10 ns min sclk to dout valid hold time t 8 4 15/45 15/35 ns min/ns max sclk falling edge to dout high impedance t 9 10 10 ns min din setup time prior to sclk falling edge t 10 5 5 ns min din hold time after sclk falling edge t 11 20 20 ns min 16th sclk falling edge to cs high t 12 1 1 s max power-up time from full shutdown/auto shutdown modes 1 sample tested @ 25c to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of av dd ) and timed from a voltage le vel of 1.6 v (see figure 2). the 3 v operating range spans from 2.7 v to 3.6 v. the 5 v operating range spans from 4.75 v to 5.25 v. 2 mark/space ratio for the sc lk input is 40/60 to 60/40. 3 measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.4 v or 0.7 v drive . 4 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteri stics is the true bus relinquish time of the part and is in dependent of the bus loading. i oh i ol 1.6v 200a 200a to output pin c l 50pf 03087-002 figure 2. load circuit for digita l output timing specifications
ad7904/ad7914/ad7924 rev. a | page 10 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating av dd to agnd ?0.3 v to +7 v v drive to agnd ?0.3 v to av dd + 0.3 v analog input voltage to agnd ?0.3 v to av dd + 0.3 v digital input voltage to agnd ?0.3 v to +7 v digital output voltage to agnd ?0.3 v to av dd + 0.3 v ref in to agnd ?0.3 v to av dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c tssop package, power dissipation 450 mw ja thermal impedance 150.4c/w (tssop) jc thermal impedance 27.6c/w (tssop) lead temperature, soldering vapor phase (60 secs) 215c infrared (15 secs) 220c esd 1.5 kv 1 transient currents of up to 100 ma will not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7904/ad7914/ad7924 rev. a | page 11 of 32 pin configuration and fu nction descriptions 1 2 3 4 5 6 7 8 din cs a gnd ref in av dd av dd sclk a gnd 16 15 14 13 12 11 10 9 v drive dout agnd v in 2 v in 3 v in 1 v in 0 agnd ad7904/ ad7914/ ad7924 top view (not to scale) 03087-003 figure 3. pin configuration table 6. pin function descriptions pin no. mnemonic function 1 sclk serial clock, logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the ad 7904/ad7914/ad7924 conversion process. 2 din data in, logic input. data to be written to the co ntrol register of the ad7904/ad7914/ad7924 is provided on this input and is clocked into the regist er on the falling edge of sclk (see the control register section). 3 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7904/ad7914/ad7924 and also frames the serial data transfer. 4, 8, 13, 16 agnd analog ground. ground reference point for all an alog circuitry on the ad7904/ad7914/ad7924. all analog input signals and any external reference signal should be referred to this agnd voltage. all agnd pins should be connected together. 5, 6 av dd analog power supply input. the av dd range for the ad7904/ad7914/ad7924 is from 2.7 v to 5.25 v. for the 0 v to 2 ref in range, av dd should be from 4.75 v to 5.25 v. 7 ref in reference input for the ad7904/ad7914/ad7924. an external reference must be applied to this input. the voltage range for the external reference is 2.5 v 1% for specified performance. 9, 10, 11, 12 v in 3, v in 2, v in 1, v in 0 analog input 0 through analog input 3. the four single -ended analog input channels are multiplexed into the on-chip track-and-hold. the analog input channel to be converted is selected using the address bits add1 and add0 of the control register. the address bits, in conjunction with the seq1 and seq0 bits, allow the sequencer to be programmed. the input range for all input channels can extend from 0 v to ref in or from 0 v to 2 ref in as selected via the range bit in the control register. any unused input channels should be connected to agnd to avoid noise pickup. 14 dout data out, logic output. the conversion result from the ad7904/ad7914/ad7924 is provid ed on this output as a serial data stream. the bits are clocked out on the falli ng edge of the sclk input. the data stream from the ad7904 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the eight bits of conversion data , followed by four trailing zeros, provided msb first. the data stream from the ad7914 consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 10 bits of conversion data, followed by two trailing zeros, provided msb first. the data stream from the ad7924 consis ts of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, provided msb first. the output coding can be selected as straight binary or twos complement via the coding bit in the control register. 15 v drive logic power supply input. the voltage supplied at this pin determines the voltage at which the serial interface of the ad7904/ad7914/ad7924 operates.
ad7904/ad7914/ad7924 rev. a | page 12 of 32 typical performance characteristics ? 50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 10 100 1000 thd (db) input frequency (khz) av dd = v drive = 2.7v av dd = v drive = 3.6v av dd = v drive = 4.75v av dd = v drive = 5.25v f sample = 1msps t a = 25c range = 0v to ref in 03087-007 ?10 ?30 ?50 ?70 ?90 ?110 0 50 100 150 200 250 300 350 400 450 500 snr (db) frequency (khz) 4096 point fft av dd = 5v f sample = 1msps f in = 50khz sinad = 71.147db thd = ?87.229db sfdr = ?90.744db 03087-004 figure 4. ad7924 dynamic performance at 1 msps figure 7. ad7924 thd vs. analog input frequency for various supply voltages at 1 msps 75 70 65 60 55 10 100 1000 sinad (db) input frequency (khz) av dd = v drive = 2.7v av dd = v drive = 3.6v av dd = v drive = 4.75v av dd = v drive = 5.25v f sample = 1msps t a = 25c range = 0v to ref in 03087-005 ? 50 ?55 ?60 ?65 ?70 ?75 ?80 ?85 ?90 10 100 1000 thd (db) input frequency (khz) r in = 1000 ? r in = 100 ? r in = 50 ? r in = 10 ? f sample = 1msps t a = 25c range = 0v to ref in av dd = 5.25v 03087-008 figure 5. ad7924 sinad vs. analog input frequency for various supply voltages at 1 msps, sclk = 20 mhz figure 8. ad7924 thd vs. analog input frequency for various source impedances 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 01 900800700600500400300200100 psrr (db) supply ripple frequency (khz) 0 0 0 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 04 3584 3072 2560 2048 1536 1024 512 inl error (lsb) code av dd = 5v 200mv p-p sine wave on av dd ref in = 2.5v, 1f capacitor t a = 25c 03087-006 0 9 6 t a = 25c av dd = v drive = 5v 03087-009 figure 6. ad7924 psrr vs. supply ripple frequency (no decoupling) figure 9. ad7924 typical inl
ad7904/ad7914/ad7924 rev. a | page 13 of 32 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 04 3584 3072 2560 2048 1536 1024 512 dnl error (lsb) code 0 9 6 t a = 25c av dd = v drive = 5v 03087-010 figure 10. ad7924 typical dnl
ad7904/ad7914/ad7924 rev. a | page 14 of 32 terminology integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error offset error is the deviation of the first code transition (00 000 to 00 001) from the ideal, that is, agnd + 1 lsb. offset error match offset error match is the difference in offset error between any two channels. gain error gain error is the deviation of th e last code transition (111 110 to 111 111) from the ideal, that is, ref in ? 1 lsb, after the offset error has been adjusted out. gain error match gain error match is the difference in gain error between any two channels. zero code error zero code error is the deviation of the midscale transition (all 0s to all 1s) from the ideal v in voltage, that is, ref in ? 1 lsb. it applies when using the twos complement output coding option with the 2 ref in input range (?ref in to +ref in biased about the ref in point). zero code error match zero code error match is the difference in zero code error between any two channels. positive gain error positive gain error is the deviation of the last code transition (011 110 to 011 111) from the ideal, that is, +ref in ? 1 lsb, after the zero code error is adjusted out. it applies when using the twos complement output coding option with the 2 ref in input range (?ref in to +ref in biased about the ref in point). positive gain error match positive gain error match is the difference in positive gain error between any two channels. negative gain error negative gain error is the deviation of the first code transition (100 000 to 100 001) from the ideal, that is, ?ref in + 1 lsb, after the zero code error is adjusted out. it applies when using the twos complement output coding option with the 2 ref in input range (?ref in to +ref in biased about the ref in point). negative gain error match negative gain error match is the difference in negative gain error between any two channels. channel-to-channel isolation channel-to-channel isolation is a measure of the level of cross- talk between channels. it is measured by applying a full-scale 400 khz sine wave signal to all three nonselected input channels and determining how much that signal is attenuated in the selected channel with a 50 khz signal. the figure is given worst case across all four channels for the ad7904/ad7914/ad7924. power supply rejection (psr) variations in power supply affect the full-scale transition but not the linearity of the converter. psr is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see figure 6 ). power supply rejection ratio (psrr) psrr is the ratio of the power in the adc output at full-scale frequency, f, to the power of a 200 mv p-p sine wave applied to the adc av dd supply of frequency f s . psrr( db ) = 10 log (pf/pfs) where: pf is the power at frequency f in the adc output. pf s is the power at frequency f s coupled onto the adc av dd supply. track-and-hold acquisition time the track-and-hold amplifier returns to track mode at the end of a conversion. track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within 1 lsb, after the end of a conversion. signal to (noise + distortion) (sinad) ratio sinad is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process: the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n-bit converter with a sine wave input is given by signal to (noise + distortion) = (6.02 n +1.76) db thus, for a 12-bit converter, sinad is 74 db, for a 10-bit converter, it is 62 db, and for an 8-bit converter, it is 50 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the funda- mental. for the ad7904/ad7914/ad7924, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log20(db) v vvvvv thd ++++ = where: v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics.
ad7904/ad7914/ad7924 rev. a | page 15 of 32 control register the control register of the ad7904/ad7914/ad7924 is a 12-bit, write-only register. data is loaded from the din pin of the ad7904/ad7914/ad7924 on the falling edge of sclk. the data is transferred on the din line at the same time that the conversion result is read from the part. the data transferred on the din line corresponds to the ad7904/ad7914/ad7924 configuration for the next conversion. this requires 16 serial clocks for every data transfer. only the information provided on the first 12 falling clock edges (after the cs falling edge) is loaded to the control register. msb denotes the first bit in the data stream. the bit functions are outlined in . table 8 table 7. channel selection add1 add0 analog input channel 0 0 v in 0 0 1 v in 1 1 0 v in 2 1 1 v in 3 table 8. control register bit functions msb lsb 11 10 9 8 7 6 5 4 3 2 1 0 write seq1 dontc dontc add1 add0 pm1 pm0 seq0 dontc range coding bit mnemonic description 11 write the value written to this bit determines whether the following 11 bits will be loaded to the control register. if this bit is set to 1, the following 11 bits will be written to the contro l register; if this bit is set to 0, the remaining 11 bits are not loaded to the control register, which remains unchanged. 10 seq1 the seq1 bit is used in conjunction with the se q0 bit to control the use of the sequencer function (see table 10 ). [9:8] dontc dont care bits. [7:6] add1, add0 the two address bits are loaded at the end of the pres ent conversion sequence and select which analog input channel is to be converted in the next serial transfer, or they may select the final channel in a consecutive sequence as described in table 10 . the selected input channel is decoded as shown in table 7 . the address bits corresponding to the conversion result are also output on dout prior to the 12 bits of data (see the serial interface section). the next channel to be converted on will be selected by the mux on the 14th sclk falling edge. [5:4] pm1, pm0 the two power management bits decode the mode of operation of the ad7904/ad7914/ad7924 as described in table 9 . 3 seq0 the seq0 bit is used in conjunction with the se q1 bit to control the use of the sequencer function (see table 10 ). 2 dontc dont care bit. 1 range this bit selects the analog input range to be used on th e ad7904/ad7914/ad7924. if it is set to 0, the analog input range will extend from 0 v to 2 ref in . if it is set to 1, the analog input range will extend from 0 v to ref in (for the next conversion). for the 0 v to 2 ref in input range, v dd = 4.75 v to 5.25 v. 0 coding this bit selects the type of output coding that the ad 7904/ad7914/ad7924 will use for the conversion result. if this bit is set to 0, the output coding for the part will be twos complement. if this bit is set to 1, the output coding from the part will be straight binary (for the next conversion). table 9. power mode selection pm1 pm0 mode description 1 1 normal operation in normal operation mode, the ad7904/ad7914/ad7924 remain in full power mode regardless of the status of any of the logic inputs. this mode allows the fastest possible throughput rate from the ad7904/ad7914/ad7924. 1 0 full shutdown in full shutdown mode, the ad7904/ad7914/ad7924 are in full shutdown with all circuitry on the device powering down. the ad7904/ad7914/ad7924 retain the information in the control register while in full shutdown. the part remains in full shutdown until these bits are changed. 0 1 auto shutdown in auto shutdown mode, the ad7904/ad7914/ad7924 auto matically enter full shutdown mode at the end of each conversion when the control register is updated. wake-up time from full shutdown is 1 s; the user should ensure that 1 s has elapsed before attempting to perform a valid conversion on the part in this mode. 0 0 invalid invalid selection. this configuration is not allowed.
ad7904/ad7914/ad7924 rev. a | page 16 of 32 sequencer operation the seq1 and seq0 bits in the control register allow the user to select a mode of operation for the sequencer function. table 10 outlines the three modes of operation of the sequencer. figure 11 shows the traditional operation of a multichannel adc, where each serial transfer selects the next channel for conversion. in this mode of operation, the sequencer function is not used. figure 12 shows how to program the ad7904/ad7914/ad7924 to continuously convert on a sequence of consecutive channels from channel 0 to a selected final channel. to exit this mode of operation and revert to the traditional mode of operation of a multichannel adc (as shown in figure 11 ), ensure that the write bit = 1 and seq1 = seq0 = 0 on the next serial transfer. table 10. sequence selection seq1 seq0 sequencer function description 0 x not used the sequencer function is not used. the analog input channel selected for each individual conversion is determined by the contents of th e channel address bits, add1 and add0, in each previous write operation. this mode of operation reflects the traditiona l operation of a multi- channel adc, without using the sequencer func tion, where each write to the ad7904/ad7914/ ad7924 selects the next channel for conversion (see figure 11 ). 1 0 used (not interrupted upon completion) the sequencer function is not interrupted upon completion of the write operation. this config- uration allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 1 1 continuous conversions this configuration is used in conjunction with the channel address bits, add1 and add0, to program continuous conversions on a consecutive sequence of channels from channel 0 to a selected final channel that is specified by the channel address bits in the control register (see figure 12 ). c s c s power on dummy conversion din: write to control register, write bit = 1, select coding, range, and power mode. select channel add1, add0 for conversion. seq1 = 0, seq0 = x dout: conversion result from previously selected channel add1, add0 din: write to control register, write bit = 1, select coding, range, and power mode. select add1, add0 for conversion. seq1 = 0, seq0 = x write bit = 1, seq1 = 0, seq0 = x 03087-011 figure 11. seq1 bit = 0, seq0 bit = x flowchart
ad7904/ad7914/ad7924 rev. a | page 17 of 32 c s power on dummy conversion din: write to control register, write bit = 1, select coding, range, and power mode. select channel add1, add0 for conversion. seq1 = 1, seq0 = 1 c s dout: conversion result from channel 0 continuously converts on a consecutive sequence of channels from channel 0 up to and including the previously selected add1, add0 in the control register write bit = 0 c s continuously converts on the selected sequence of channels but will allow range, coding, and so forth, to change in the control register without interrupting the sequence, provided seq1 = 1, seq0 = 0 write bit = 1, seq1 = 1, seq0 = 0 03087-012 figure 12. seq1 bit = 1, seq0 bit = 1 flowchart
ad7904/ad7914/ad7924 rev. a | page 18 of 32 circuit information the ad7904/ad7914/ad7924 are, respectively, 8-bit, 10-bit, and 12-bit, high speed, 4-channel, single-supply adcs. the parts can be operated from a 2.7 v to 5.25 v supply. when operated from either a 5 v or 3 v supply, the ad7904/ad7914/ad7924 are capable of throughput rates of 1 msps when provided with a 20 mhz clock. the ad7904/ad7914/ad7924 provide the user with an on-chip track-and-hold adc and serial interface housed in a 16-lead tssop package. the ad7904/ad7914/ad7924 each have four single-ended input channels with a channel sequencer, allowing the user to select a channel sequence through which the adc can cycle with each consecutive cs falling edge. the serial clock input accesses data from the part, controls the transfer of data written to the adc, and provides the clock source for the succes- sive approximation adc. the analog input range for the ad7904/ ad7914/ad7924 is 0 v to ref in or 0 v to 2 ref in , depending on the status of bit 1 in the control register. for the 0 v to 2 ref in range, the part must be operated from a 4.75 v to 5.25 v supply. the ad7904/ad7914/ad7924 provide flexible power management options to allow the user to achieve the best power performance for a given throughput rate. these options are selected by pro- gramming the power management bits, pm1 and pm0, in the control register. converter operation the ad7904/ad7914/ad7924 are 8-, 10-, and 12-bit sar adcs, respectively, based around a capacitive dac. the ad7904/ ad7914/ad7924 can convert analog input signals in the range of 0 v to ref in or 0 v to 2 ref in . figure 13 and figure 14 show simplified schematics of the adc. the ad7904/ad7914/ ad7924 include control logic, the sar adc, and a capacitive dac, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. figure 13 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the sampling capacitor acquires the signal on the selected v in channel. agnd a b sw1 sw2 comparator 4k ? v in 0 v in 3 capacitive dac control logic 03087-013 figure 13. adc acquisition phase when the adc starts a conversion (see figure 14 ), sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc output code. figure 16 and figure 17 show the adc transfer functions. agnd a b sw1 sw2 comparator 4k ? v in 0 v in 3 capacitive dac control logic 03087-014 figure 14. adc conversion phase analog input figure 15 shows an equivalent circuit of the analog input structure of the ad7904/ad7914/ad7924. the two diodes, d1 and d2, provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mv. this will cause these diodes to become forward-biased and start conducting current into the substrate. the maximum current that these diodes can conduct without causing irreversible damage to the part is 10 ma. capacitor c1 in figure 15 is typically about 4 pf and can primarily be attributed to pin capacitance. the resistor, r1, is a lumped component made up of the on resistance of a track-and-hold switch and the on resistance of the input multiplexer. the total resistance is typically about 400 . capacitor c2 is the adc sampling capacitor and has a capacitance of 30 pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by use of a low-pass rc filter on the relevant analog input pin. in applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd increases as the source impedance increases, and performance will degrade (see figure 8 ). c1 4pf c2 30pf r1 d1 d2 a v dd v in conversion phase: switch open track phase: switch closed 03087-015 figure 15. equivalent analog input circuit
ad7904/ad7914/ad7924 rev. a | page 19 of 32 adc transfer function the output coding of the ad7904/ad7914/ad7924 is either straight binary or twos complement, depending on the status of the lsb in the control register. the designed code transitions occur at successive lsb values (that is, 1 lsb, 2 lsbs, and so on). for the 0 v to ref in input range, the lsb size is ref in /256 for the ad7904, ref in /1024 for the ad7914, and ref in /4096 for the ad7924. for the 0 v to 2 ref in input range, the lsb size is 2 ref in /256 for the ad7904, 2 ref in /1024 for the ad7914, and 2 ref in /4096 for the ad7924. the ideal transfer charac- teristic for the ad7904/ad7914/ad7924 when straight binary coding is selected is shown in figure 16 ; the ideal transfer characteristic for the ad7904/ad7914/ad7924 when twos complement coding is selected is shown in figure 17 . adc code 000?000 0v analog input 111?111 000?001 000?010 111?110 ? ? 111?000 ? 011?111 ? ? 1lsb +v ref ? 1lsb notes 1. v ref is either ref in or 2 ref in . 1lsb = v ref /256 ad7904 1lsb = v ref /1024 ad7914 1lsb = v ref /4096 ad7924 03087-016 figure 16. straight binary transfer characteristic 1lsb = 2 v ref /256 ad7904 1lsb = 2 v ref /1024 ad7914 1lsb = 2 v ref /4096 ad7924 adc code analog input 100?000 011?111 100?001 100?010 011?110 ? ? 000?001 111?111 ? ? 000?000 ?v ref + 1lsb +v ref ? 1lsb v ref ? 1lsb 0 3087-017 figure 17. twos complement transfer characteristic with 0 v to 2 ref in input range handling bipolar input signals figure 18 shows how the combination of the 0 v to 2 ref in input range and the twos complement output coding scheme is particularly useful for handling bipolar input signals. if the bipolar input signal is biased about ref in and twos complement output coding is selected, ref in becomes the zero code point, ?ref in is negative full scale, and +ref in becomes positive full scale, with a dynamic range of 2 ref in . r3 r2 r4 v in 0 ref in v in 3 v av dd dout ref in +ref in ?ref in 011?111 000?000 100?000 0 v v r1 r1 = r2 = r3 = r4 v dd v drive ad7904/ ad7914/ ad7924 v ref 0.1f twos complement (= 0v) (= 2 ref in ) v dd dsp/ micro- processor 03087-018 figure 18. handling bipolar signals
ad7904/ad7914/ad7924 rev. a | page 20 of 32 typical connection diagram figure 19 shows a typical connection diagram for the ad7904/ ad7914/ad7924. in this setup, the agnd pin is connected to the analog ground plane of the system. in figure 19 , the ref in pin is connected to a decoupled 2.5 v supply from a reference source, the ad780 , to provide an analog input range of 0 v to 2.5 v (if the range bit is set to 1) or 0 v to 5 v (if the range bit is set to 0). although the ad7904/ad7914/ad7924 are connected to a v dd of 5 v, the serial interface is connected to a 3 v microprocessor. the v drive pin of the ad7904/ad7914/ad7924 is connected to the same 3 v supply as the microprocessor to allow a 3 v logic interface (see the digital inputs section). the conversion result is output in a 16-bit word. this 16-bit data stream consists of two leading zeros, two address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data for the ad7924 (10 bits of data for the ad7914 and 8 bits of data for the ad7904, each followed by two and four trailing zeros, respectively). for applications where power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance (see the modes of operation section). notes 1. all unused input channels should be connected to agnd. v in 0 v in 3 agnd sclk dout cs din ad7904/ ad7914/ ad7924 0v to re f in ref in v drive av dd 0.1f 10f 5 v supply se ri al interface 0.1f 0.1f 10f micro- controller/ micro- processor 2.5v ad780 3v supply 0 3087-019 figure 19. typical connection diagram analog input selection any one of four analog input channels can be selected for conversion by programming the multiplexer with the address bits add1 and add0 in the control register. the channel configurations are shown in table 7 . the ad7904/ad7914/ad7924 can also be configured to auto- matically cycle through a number of selected channels. the sequencer feature is accessed via the seq1 and seq0 bits in the control register (see table 10 ). the ad7904/ad7914/ad7924 can be programmed to continuously convert on a number of consecutive channels in ascending order from channel 0 to a selected final channel as determined by the channel address bits, add1 and add0. this is possible if the seq1 and seq0 bits are set to 11. the next serial transfer will then act on the sequence programmed by executing a conversion on channel 0. the next serial transfer will result in a conversion on channel 1, and so on, until the channel selected via the address bits, add1 and add0, is reached. it is not necessary to write to the control register again after a sequence operation has been initiated. to ensure that the control register is not accidently overwritten or the sequence operation interrupted, the write bit must be set to 0 or the din line must be tied low. if the control register is written to at any time during the sequence, the seq1 and seq0 bits must be set to 10 to avoid interrupting the automatic conversion sequence. this pattern continues until the ad7904/ad7914/ad7924 are written to and the seq1 and seq0 bits are configured with a bit combination other than 10, resulting in the termination of the sequence. if the sequence is uninterrupted (write bit = 0, or write bit = 1 and seq1 and seq0 bits are set to 10), then upon completion of the sequence, the ad7904/ad7914/ad7924 sequencer returns to channel 0 and restarts the sequence. regardless of the channel selection method used, the 16-bit word output from the ad7924 during each conversion always contains two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit con- version result; the ad7914 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros; the ad7904 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros (see the serial interface section).
ad7904/ad7914/ad7924 rev. a | page 21 of 32 digital inputs the digital inputs applied to the ad7904/ad7914/ad7924 can go to 7 v and are not restricted by the av dd + 0.3 v limit on the analog inputs. because the sclk, din, and cs inputs are not restricted by the av dd + 0.3 v limit, power supply sequencing issues are avoided. if cs , din, or sclk is applied before av dd , there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 v is applied prior to av dd . v drive the ad7904/ad7914/ad7924 also include the v drive feature. v drive controls the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7904/ad7914/ad7924 are operated with a v dd of 5 v, the v drive pin can be powered from a 3 v supply. the ad7904/ad7914/ad7924 have better dynamic performance with a v dd of 5 v while still being able to interface to 3 v processors. care should be taken to ensure that v drive does not exceed av dd by more than 0.3 v (see the absolute maximum ratings section). reference an external reference source should be used to supply the 2.5 v reference to the ad7904/ad7914/ad7924. errors in the refer- ence source result in gain errors in the ad7904/ad7914/ ad7924 transfer function and add to the specified full-scale errors of the part. a capacitor of at least 0.1 f should be placed on the ref in pin. suitable reference sources for the ad7904/ ad7914/ad7924 include the ad780 , ref193 , and ad1582 . if 2.5 v is applied to the ref in pin, the analog input range can be either 0 v to 2.5 v or 0 v to 5 v, depending on the setting of the range bit in the control register.
ad7904/ad7914/ad7924 rev. a | page 22 of 32 modes of operation the ad7904/ad7914/ad7924 have three modes of operation. these modes are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing application require- ments. the mode of operation of the ad7904/ad7914/ad7924 is controlled by the power management bits, pm1 and pm0, in the control register (see table 9 ). when power supplies are first applied to the ad7904/ad7914/ad7924, care should be taken to ensure that the part is placed in the required mode of operation (see the powering up the ad7904/ad7914/ad7924 section). normal mode (pm1 = pm0 = 1) normal mode is intended for the fastest throughput rate perfor- mance. because the ad7904/ad7914/ad7924 remain fully powered up at all times, the user does not need to worry about power-up times. figure 20 shows the general diagram of the operation of the ad7904/ad7914/ad7924 in this mode. notes 1. control register data is loaded on first 12 sclk cycles. 1 12 cs sclk dout din 16 data in to control register 2 leading zeros + 2 channel identifier bits + conversion result 03087-020 figure 20. normal mode operation the conversion is initiated on the falling edge of cs ; the track- and-hold enters hold mode as described in the section. the data presented to the ad7904/ad7914/ad7924 on the din line during the first 12 clock cycles of the data transfer is loaded into the control register (provided that the write bit is set to 1). in normal mode, the part remains fully powered up at the end of the conversion as long as the pm1 and pm0 bits are set to 1 in the write transfer during that same conversion. to ensure continued operation in normal mode, pm1 and pm0 must both be set to 1 on every data transfer, assuming that a write operation is taking place. if the write bit is set to 0, the power management bits are left unchanged, and the part remains in normal mode. serial interface sixteen serial clock cycles are required to complete the conversion and to access the conversion result. the track-and-hold returns to track mode on the 14th sclk falling edge. cs may then idle high until the next conversion or it may idle low until some time prior to the next conversion (effectively idling cs low). when a data transfer is complete (dout has returned to three- state), another conversion can be initiated after the quiet time, t quiet , has elapsed by bringing cs low again. full shutdown mode (pm1 = 1, pm0 = 0) in full shutdown mode, all internal circuitry on the ad7904/ ad7914/ad7924 is powered down. the part retains information in the control register during full shutdown. the ad7904/ad7914/ ad7924 remain in full shutdown until the power management bits in the control register, pm1 and pm0, are changed. if a write to the control register occurs while the part is in full shutdown, and the power management bits are changed to pm0 = pm1 = 1 (that is, normal mode), the part will begin to power up on the cs rising edge. the track-and-hold, which was in hold mode while the part was in full shutdown, returns to track mode on the 14th sclk falling edge. to ensure that the part is fully powered up, t power-up (t 12 ) should have elapsed before the next cs falling edge. shows the general diagram for this sequence. figure 21 auto shutdown mode (pm1 = 0, pm0 = 1) in auto shutdown mode, the ad7904/ad7914/ad7924 auto- matically enter shutdown at the end of each conversion when the control register is updated. when the part is in auto shutdown, the track-and-hold is in hold mode. figure 22 shows the general diagram of the operation of the ad7904/ad7914/ad7924 in this mode. in auto shutdown mode, all internal circuitry on the ad7904/ ad7914/ad7924 is powered down. the part retains information in the control register during auto shutdown. the ad7904/ ad7914/ad7924 remain in shutdown until the next cs falling edge that it receives. on this cs falling edge, the track-and-hold, which was in hold mode while the part was in shutdown, returns to track mode. wake-up time from auto shutdown is 1 s max- imum, and the user should ensure that 1 s has elapsed before attempting a valid conversion. when running the ad7904/ad7914/ad7924 with a 20 mhz clock, one 16 sclk dummy cycle should be sufficient to ensure that the part is fully powered up. during this dummy cycle, the contents of the control register should remain unchanged; therefore, the write bit should be set to 0 on the din line. this dummy cycle effectively halves the throughput rate of the part, with every other conversion result being valid. in auto shutdown mode, the power consumption of the part is greatly reduced because the part enters shutdown at the end of each conversion. when the control register is programmed to move into auto shutdown mode, it does so at the end of the con- version. the user can move the adc in and out of the low power state by controlling the cs signal.
ad7904/ad7914/ad7924 rev. a | page 23 of 32 sclk dout din cs 14 16 1 14 16 1 t 12 part is in full shutdown part begins to power up on cs rising edge as pm1 = pm0 = 1 the part is fully powered up once t power up has elapsed channel identifier bits + conversion result data in to control register data in to control register control register is loaded on the first 12 clocks. pm1 = 1, pm0 = 1 to keep the part in normal mode, load pm1 = pm0 = 1 in control register 03087-021 figure 21. full shut down mode operation sclk dout din cs 11 6 12 1 16 12 1 16 12 part enters shutdown on cs rising edge as pm1 = 0, pm0 = 1 part begins to power up on cs falling edge part is fully powered up part enters shutdown on cs rising edge as pm1 = 0, pm0 = 1 channel identifier bits + conversion result channel identifier bits + conversion result invalid data data in to control register data in to control register control register is loaded on the first 12 clocks, pm1 = 0, pm0 = 1 control register contents should not change, write bit = 0 to keep part in this mode, load pm1 = 0, pm0 = 1 in control register or set write bit = 0 dummy conversion 0 3087-022 figure 22. auto shut down mode operation powering up the ad7904/ad7914/ad7924 when supplies are first applied to the ad7904/ad7914/ad7924, the adc may power up in any of the operating modes of the part. to ensure that the part is placed into the required operating mode, the user should perform a dummy cycle operation as shown in figure 23 , figure 24 , and figure 25 . the dummy conversion operation must be performed to place the part into the desired mode of operation. to ensure that the part is in normal mode, this dummy cycle operation can be performed with the din line tied high, that is, the pm1 and pm0 bits are set to 11 (depending on other required settings in the control register). however, the minimum power-up time of 1 s must be allowed from the rising edge of cs , where the control register is updated, before attempting the first valid conversion. this power-up time allows for the possibility that the part was initially powered up in shutdown mode. if the desired mode of operation is full shutdown, one dummy cycle is required after supplies are applied. in this dummy cycle, the user simply sets the power management bits, pm1 and pm0, to 10 and, upon the rising edge of cs at the end of that serial transfer, the part enters full shutdown mode. if the desired mode of operation after supplies are applied is auto shutdown mode, two dummy cycles are required: the first dummy cycle with din tied high, and the second to set the power management bits, pm1 and pm0, to 01. on the second cs rising edge after the supplies are applied, the control register contains the correct information and the part enters auto shutdown mode as programmed. if power consumption is of critical concern, then in the first dummy cycle, the user can set pm1 and pm0 to 10, that is, full shutdown mode, and then place the part into auto shutdown mode in the second dummy cycle. for illustration purposes, is shown with din tied high on the first dummy cycle in this case. figure 25 figure 23 , figure 24 , and figure 25 show the required dummy cycles after supplies are applied for normal mode, full shutdown mode, and auto shutdown mode, respectively.
ad7904/ad7914/ad7924 rev. a | page 24 of 32 sclk dout din cs 11 6 14 1 16 14 part is in unknown mode after power-on allow t power to elapse if in shutdown at power-on, part begins to power up on cs rising edge as pm1 = pm0 = 1 t 12 din line high for first dummy conversion to keep the part in normal mode, load pm1 = pm0 = 1 in control register invalid data channel identifier bits + conversion result data in to control register 03087-023 figure 23. placing the ad7904/ad7914/ad7924 into normal mode after supplies are first applied sclk dout din cs part is in unknown mode after power-on part enters shutdown on cs rising edge as pm1 = 1, pm0 = 0 11 4 invalid data data in to control register control register is loaded on the first 12 clocks. pm1 = 1, pm0 = 0 03087-024 1 6 figure 24. placing the ad7904/ad7914/ad7924 into full shutdown mode after supplies are first applied sclk dout din cs part enters auto shutdown on cs rising edge as pm1 = 0, pm0 = 1 11 4 1 6 11 4 1 6 part is in unknown mode after power-on invalid data invalid data data in to control register din line high for first dummy conversion control register is loaded on the first 12 clocks. pm1 = 0, pm0 = 1 03087-025 figure 25. placing the ad7904/ad7914/ad7924 into au to shutdown mode after supplies are first applied
ad7904/ad7914/ad7924 rev. a | page 25 of 32 power vs. throughput rate by operating the ad7904/ad7914/ad7924 in auto shutdown mode, the average power consumption of the adc decreases at lower throughput rates. figure 26 shows how, as the throughput rate is reduced, the part remains in its shutdown state longer, and the average power consumption over time drops accordingly. for example, if the ad7924 is operated in continuous sampling mode with a throughput rate of 100 ksps and an sclk of 20 mhz (av dd = 5 v), and the device is placed into auto shutdown mode (pm1 = 0 and pm0 = 1), the power consumption is calculated as described in this section. the maximum power dissipation during normal operation is 13.5 mw (av dd = 5 v). if the power-up time from auto shutdown is one dummy cycle, that is, 1 s, and the remaining conversion time is another cycle, that is, 1 s, then the ad7924 can be said to dissipate 13.5 mw for 2 s during each conversion cycle. for the remainder of the conversion cycle, 8 s, the part remains in shutdown. the ad7924 can be said to dissipate 2.5 w for the remaining 8 s of the conversion cycle. if the throughput rate is 100 ksps, the cycle time is 10 s and the average power dissipated during each cycle is ((2/10) 13.5 mw) + ((8/10) 2.5 w) = 2.702 mw. figure 26 shows the maximum power vs. throughput rate when using the auto shutdown mode with 5 v and 3 v supplies. 10 0.01 0.1 1 0 300 250 200 150 100 50 power (mw) throughput (ksps) 3 5 0 av dd = 5v av dd = 3v 03087-026 figure 26. ad7924 power vs. throughput rate serial interface figure 27 , figure 28 , and figure 29 show the detailed timing diagrams for serial interfacing to the ad7904, ad7914, and ad7924, respectively. the serial clock provides the conversion clock and also controls the transfer of information to and from the ad7904/ad7914/ad7924 during each conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts the track-and-hold into hold mode and takes the bus out of three-state; the analog input is sampled at this point. the conversion is also initiated at this point and requires 16 sclk cycles to complete. the track-and-hold returns to track mode on the 14th sclk falling edge, as shown by point b in , , and . on the 16th sclk falling edge, the dout line returns to three-state. if the rising edge of figure 27 figure 28 figure 29 cs occurs before 16 sclks have elapsed, the conversion is terminated, the dout line returns to three-state, and the control register is not updated; otherwise, dout returns to three-state on the 16th sclk falling edge, as shown in , , and . figure 27 figure 28 figure 29 sixteen serial clock cycles are required to perform the conversion process and to access data from the ad7904/ad7914/ad7924. for the ad7904/ad7914/ad7924, the 8/10/12 bits of data are preceded by two leading zeros and the two channel address bits, add1 and add0, which identify the channel that the result corresponds to. cs going low clocks out the first leading zero to be read in by the microcontroller or dsp on the first falling edge of sclk. the first falling edge of sclk also clocks out the second leading zero to be read in by the microcontroller or dsp on the second sclk falling edge, and so on. the two address bits and the 8/10/12 data bits are then clocked out by subsequent sclk falling edges beginning with the first address bit, add1; thus, the second falling clock edge on the serial clock has the second leading zero provided and also clocks out the address bit add1. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. the writing of information to the control register takes place on the first 12 falling edges of sclk in a data transfer, assuming that the msb (the write bit) has been set to 1. the ad7904 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 8-bit conversion result and four trailing zeros. the ad7914 outputs two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 10-bit conversion result and two trailing zeros. the 16-bit word read from the ad7924 always contains two leading zeros, two channel address bits that the conversion result corresponds to, followed by the 12-bit conversion result.
ad7904/ad7914/ad7924 rev. a | page 26 of 32 sclk dout din cs 123456111213141516 b three- state zero three- state 4 trailing zeros dontc dontc zero db0 zero zero zero zero add1 add0 db7 db6 dontc dontc coding seq1 dontc dontc add1 add0 write 2 identification bits t 9 t 2 t 3 t 4 t 7 t 6 t convert t 5 t 8 t quiet t 11 t 10 03087-027 figure 27. ad7904 serial interface timing diagram sclk dout din cs 123456111213141516 b three- state zero three- state 2 trailing zeros dontc dontc db1 db2 db0 zero zero zero add1 add0 db9 db8 dontc dontc coding seq1 dontc dontc add1 add0 write 2 identification bits t 9 t 2 t 3 t 4 t 7 t 6 t convert t 5 t 8 t quiet t 11 t 10 03087-028 figure 28. ad7914 serial interface timing diagram sclk dout din cs 123456111213141516 b three- state zero three- state dontc dontc db3 db4 db2 db1 db0 zero add1 add0 db11 db10 dontc dontc coding seq1 dontc dontc add1 add0 write 2 identification bits t 9 t 2 t 3 t 4 t 7 t 6 t convert t 5 t 8 t quiet t 11 t 10 03087-029 figure 29. ad7924 serial interface timing diagram
ad7904/ad7914/ad7924 rev. a | page 27 of 32 applications information microprocessor interfacing the serial interface of the ad7904/ad7914/ad7924 allows the part to be directly connected to a range of different microprocessors. this section explains how to interface the ad7904/ad7914/ad7924 to some of the more common microcontroller and dsp serial interface protocols. ad7904/ad7914/ad7924 to tms320c541 the serial interface of the tms320c541 uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the ad7904/ ad7914/ad7924. the cs input allows easy interfacing between the tms320c541 and the ad7904/ad7914/ad7924 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode with internal clkx0 (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control (spc) register must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the connection diagram is shown in . note that for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 provide equidistant sampling. the v drive pin of the ad7904/ad7914/ad7924 takes the same supply voltage as the tms320c541. this allows the adc to operate at a higher voltage than the serial interface, that is, the tms320c541, if necessary. figure 30 *additional pins removed for clarity. tms320c541* clkx clkr sclk fsx fsr cs dr dout dt din v drive ad7904/ ad7914/ ad7924* v dd 0 3087-030 figure 30. interfacing to the tms320c541 ad7904/ad7914/ad7924 to adsp-218x the adsp-218x family of dsps interfaces directly to the ad7904/ad7914/ad7924 without any glue logic required. the v drive pin of the ad7904/ad7914/ad7924 takes the same supply voltage as the adsp-218x. this allows the adc to operate at a higher voltage than the serial interface, that is, the adsp-218x, if necessary. the sport0 control register of the adsp-218x should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data-words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0 itfs = 1 the connection diagram is shown in figure 31 . the adsp-218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alter- nate framing mode and the sport0 control register is set up as described. the frame synchronization signal generated on the tfs is tied to cs and, as with all signal processing applications, equidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc, and under certain conditions equidistant sampling may not be achieved. *additional pins removed for clarity. adsp-218x* sclk sclk v drive ad7904/ ad7914/ ad7924* dt din dr dout v dd rfs tfs cs 0 3087-031 figure 31. interfacing to the adsp-218x the timer register, for example, is loaded with a value that provides an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and thus the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given (that is, ax0 = tx0), the state of the sclk is checked. the dsp waits until sclk goes high, low, and high again before transmission starts. if the timer and sclk values are chosen in such a way that the instruction to transmit occurs on or near the rising edge of sclk, the data may be transmitted or it may wait until the next clock edge. for example, if the adsp-2189 has a 20 mhz crystal so that its master clock frequency is 40 mhz, then the master cycle time is 25 ns. if the sclkdiv register is loaded with the value 3, then an sclk of 5 mhz is obtained and eight master clock periods elapse for every one sclk period.
ad7904/ad7914/ad7924 rev. a | page 28 of 32 depending on the throughput rate selected, if the timer register is loaded with a value such as 803 (803 + 1 = 804), then 100.5 sclks will occur between interrupts and subsequently between transmit instructions. this setup results in nonequidistant sampling because the transmit instruction occurs on an sclk edge. if the number of sclks between interrupts is a whole integer value n, equidistant sampling is implemented by the dsp. ad7904/ad7914/ad7924 to dsp563xx the connection diagram in figure 32 shows how the ad7904/ ad7914/ad7924 can be connected to the essi (synchronous serial interface) of the dsp563xx family of dsps from motorola. each essi (two on board) is operated in synchronous mode (syn bit in crb = 1) with internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in crb). normal operation of the essi is selected by setting mod = 0 in the crb. set the word length to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. the fsp bit in the crb should be set to 1 so that the frame sync is negative. note that for signal processing applications, it is imperative that the frame synchroni- zation signal from the dsp563xx provide equidistant sampling. in the example shown in figure 32 , the serial clock is taken from the essi so the sck0 pin must be set as an output (sckd = 1). the v drive pin of the ad7904/ad7914/ad7924 takes the same supply voltage as the dsp563xx. this allows the adc to operate at a higher voltage than the serial interface, that is, the dsp563xx, if necessary. *additional pins removed for clarity. dsp563xx* v drive ad7904/ ad7914/ ad7924* sc2 din srd dout sck sclk v dd std cs 0 3087-032 figure 32. interfacing to the dsp563xx grounding and layout the ad7904/ad7914/ad7924 have very good immunity to noise on the power supplies (see figure 6 ). however, care should be taken with regard to grounding and layout. the pcb that houses the ad7904/ad7914/ad7924 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it provides the best shielding. all four agnd pins of the ad7904/ ad7914/ad7924 should be sunk in the agnd plane. digital and analog ground planes should be joined at only one place. if the ad7904/ad7914/ad7924 are in a system where multiple devices require an agnd-to-dgnd connection, the connection should still be made at one point only: a star ground point established as close as possible to the ad7904/ad7914/ad7924. avoid running digital lines under the device because these lines couple noise onto the die. the analog ground plane should be allowed to run under the ad7904/ad7914/ad7924 to avoid noise coupling. the power supply lines to the ad7904/ad7914/ ad7924 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum capacitors in parallel with 0.1 f capacitors to agnd. to achieve the best performance from these decoupling components, place them as close as possible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types or surface-mount types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
ad7904/ad7914/ad7924 rev. a | page 29 of 32 evaluating ad7904/ad7914/ad7924 performance the recommended layout for the ad7904/ad7914/ad7924 is outlined in the evaluation board for the ad7904/ad7914/ ad7924. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the evaluation board controller (eval-control-brd2). the evaluation board controller can be used in conjunction with the ad7904/ad7914/ad7924 evaluation board, as well as with many other analog devices, inc., evaluation boards ending in the cb designator, to demonstrate and evaluate the ac and dc performance of the ad7904/ad7914/ad7924. the software allows the user to perform ac (fast fourier transform) and dc (histogram of codes) tests on the ad7904/ ad7914/ad7924. the software and documentation are on a cd shipped with the evaluation board.
ad7904/ad7914/ad7924 rev. a | page 30 of 3 2 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 33. 16-lead thin shrink small outline package (tssop) (ru-16) dimensions shown in millimeters ordering guide model temperature range linearity error (lsb) 1 package option package description ad7904bru ?40c to +85c 0.2 ru-16 16-lead tssop AD7904BRUZ 2 ?40c to +85c 0.2 ru-16 16-lead tssop AD7904BRUZ-reel 2 ?40c to +85c 0.2 ru-16 16-lead tssop AD7904BRUZ-reel7 2 ?40c to +85c 0.2 ru-16 16-lead tssop ad7914bru-reel ?40c to +85c 0.5 ru-16 16-lead tssop ad7914bruz 2 ?40c to +85c 0.5 ru-16 16-lead tssop ad7914bruz-reel7 2 ?40c to +85c 0.5 ru-16 16-lead tssop ad7924bru ?40c to +85c 1 ru-16 16-lead tssop ad7924bruz 2 ?40c to +85c 1 ru-16 16-lead tssop ad7924bruz-reel 2 ?40c to +85c 1 ru-16 16-lead tssop ad7924bruz-reel7 2 ?40c to +85c 1 ru-16 16-lead tssop eval-ad79x4cbz 2 , 3 evaluation board eval-control-brd2 4 controller board 1 linearity error refers to integral linearity error. 2 z = rohs compliant part. 3 this board can be used as a standalone evaluation board or in conjunction with the evaluation controller board for evaluation/ demonstration purposes. the board comes with one chip each of the ad7904, ad7914, and ad7924. 4 this board is a complete unit, allowing a pc to control and communicate with all anal og devices evaluation boards ending in th e cb designator. to order a complete evaluation kit, you need to order the specific adc evaluation board, for example, the eval-ad79x4cbz, the eval-control-brd2, an d a 12 v ac transformer. see the relevant evaluation board technical note for more information.
ad7904/ad7914/ad7924 rev. a | page 31 of 3 2 notes
ad7904/ad7914/ad7924 rev. a | page 32 of 32 notes ?2002C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03087-0-2/09(a)

▲Up To Search▲

Price & Availability of AD7904BRUZ

	To Download AD7904BRUZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .